1. Field of the Invention
The present invention relates to a video signal processing apparatus and a video signal processing method wherein processing in the direction of the time axis is performed by delaying only the effective picture period of standard video signal, and also relates to a video signal recording/reproduction apparatus incorporating such a video signal processing apparatus.
2. Description of the Related Art
An apparatus for improving video signal quality includes a video signal processing apparatus of the type that performs arithmetic operations in the direction of the time axis, for example, a three-dimensional luminance and chrominance signal separation filter, video signal noise suppressor, and field or frame interpolation apparatus. FIG. 1 is a block diagram showing a prior art configuration of such a video signal processing apparatus, and FIG. 2 is a schematic diagram showing a video signal in three-dimensional space. In FIG. 2, the direction of the time axis in the video signal is the direction of t axis, which is sometimes called the field direction or the frame direction. To perform arithmetic operations in the direction of the time axis, it is necessary to delay the video signal using a storage device such as a memory circuit; in this case, if the circuit is configured so that only the effective picture period, excluding the retrace interval, is stored in the memory circuit, the required capacity of the memory circuit can be reduced. The video signal processing apparatus of the prior art shown in FIG. 1 is an example of such a configuration wherein only the effective picture period is stored in the memory circuit and arithmetic operations are performed in the direction of the time axis.
In FIG. 1, the numeral 1 indicates an input terminal via which a video signal is inputted, and 2 designates an output terminal via which the video signal after arithmetic operations is outputted. The video signal, input via the inputted terminal 1, is fed to a synchronizing signal separation circuit 8, a memory circuit 10, and an arithmetic circuit 11, respectively. The synchronizing signal separation circuit 8 separates a synchronizing signal from the input video signal, and supplies the separated synchronizing signal to a reset circuit 6. The reset circuit 6 outputs a reset pulse to a counter circuit 7 in synchronization with the synchronizing signal. The counter circuit 7 performs a counting action upon reception of the reset pulse, and supplies the count value to a memory control circuit 9. The memory control circuit 9 controls the memory circuit, 10 in accordance with the count value. The memory circuit 10 is a storage circuit having the capacity necessary for delaying the input video signal in the direction of the time axis, and under the control of the memory control circuit 9, supplies the video signal delayed in the direction of the time axis to the arithmetic circuit 11. The arithmetic circuit 11 performs arithmetic operations in the direction of the time axis on the video signal supplied via the input, terminal 1 and the delayed video signal outputted from the memory circuit 10, and outputs the thus processed video signal at the output terminal 2.
Next, the operation of the above apparatus will be described below. The description below concerns a case where the vertical retrace interval is not stored in the memory circuit 10. The standard video signal is applied at the input terminal 1. The standard video signal is a video signal for which the relations defined by the following equations (1) and (2) hold among the color subcarrier frequency fsc, horizontal synchronizing signal frequency fh, and vertical synchronizing frequency fv. EQU fsc=(455/2)fh Equation (1) EQU fh=(525/2)fv Equation (2)
In the video signal processing apparatus shown in FIG. 1, a pulse signal synchronized to the color subcarrier of the input video signal and having a frequency equal to a multiple thereof is used as the clock.
FIG. 3 is a timing chart illustrating the operation of the various circuit blocks. The video signal, inputted via the input terminal 1, is fed to the synchronizing signal separation circuit 8, the memory circuit 10, and the arithmetic circuit 11, respectively. The synchronizing signal separation circuit 8 separates a vertical synchronizing signal from the input video signal, and supplies the separated vertical synchronizing signal to the reset circuit 6. In synchronism with the vertical synchronizing signal, the reset circuit 6 outputs a reset pulse to reset the counter circuit 7. The counter circuit 7, which is controlled by the reset pulse thus applied, performs a counting action and supplies the count value to the memory control circuit 9. In accordance with the count value from the counter circuit 7, the memory control circuit 9 outputs a control signal for a predetermined portion of the video signal to be written into the memory circuit 10, and a control signal for delaying the video signal in the direction of time axis when read out of the memory circuit 10; these control signals are supplied to the memory circuit 10. Then, in the arithmetic circuit 11, arithmetic operations in the direction of the time axis are performed between the input video signal from the input terminal 1 and the video signal from the memory circuit 10 delayed in the direction of the time axis, and the resulting video signal is outputted at the output terminal 2.
FIG. 4 is a diagram showing the positional relationship in the direction of the time axis between the input video signal and the video signal outputted from the memory circuit 10. In FIG. 4, arithmetic operations in the direction of time axis are arithmetic operations performed between a and a', between b and b' and between c and c', respectively. For all arithmetic data, the time spacing between arithmetic data is equal to an integral multiple of the field period 1/fv. The arithmetic operations performed here include, for example, three-dimensional luminance and chrominance signal separation, noise elimination, etc.
In the above-described configuration of the prior art video signal processing apparatus in which, to reduce the capacity of the memory circuit 10 for storing the video signal, arithmetic operations in the direction of the time axis are performed by delaying only the effective picture period of standard video signal, the portion of the video signal to be written into the memory circuit 10 is determined on the basis of the synchronizing signal that the synchronizing signal separation circuit separates from the video signal. Generally, when separating the synchronizing signal from the video signal in the synchronizing signal separation circuit 8, variations in the timing, called jitter, occur due to noise or waveform distortion superposed on the video signal, causing variations in the cycle of the synchronizing signal. Since the position of the video signal to be written into the memory circuit 10 is determined on the basis of the synchronizing signal, as described above, variations in the cycle of the synchronizing signal result in variations of the write position. FIG. 5 shows the positional relationship in the direction of the time axis between the input video signal and the video signal outputted from the memory circuit 10 when jitter is caused on the synchronizing signal. Normally, the output video signal should be stored in the memory circuit 10 as a', b', c' . . . , but when jitter is caused on the synchronizing signal, the signal is stored as b', c', d' . . . , in which case arithmetic operations are performed between a and b', between b and c', and between c and d'. The resulting problem is that the time spacing between the input video signal and the video signal outputted from the memory circuit 10 is no longer equal to an integral multiple of the field period, and therefore, arithmetic operations between the input video signal and the video signal outputted from the memory circuit 10 are not performed in the correct time axis direction in the arithmetic circuit 11.